For example, in order to detect a permanent fault caused in the manufacturing process of a circuit, or in order to detect and correct a data error caused by a software error or the like in which data is inverted as voltage fluctuates during the use of a product or as an c-ray or a neutron ray enter a circuit, there are some cases in which the circuit is provided with another circuit for detecting and correcting the data error. This function of detecting and correcting a data error is referred to as the RAS (Reliability, Availability and Serviceability) function or the like.
In order to detect and correct a data error caused in a circuit, it is necessary that the data on which error detection and error correction are performed be made redundant and that the circuit be provided with another circuit for realizing the RAS function. However, the size and content of the redundant portion added to the data vary depending on the purpose of detecting and correcting a data error.
For example, 1 parity bit is given to 8 bits of information data. Such a parity bit is produced by performing an XOR (exclusive-OR) operation for each bit of the information data. At the same time, an error detector is provided for performing an XOR operation between each bit of the information data and a parity check bit. Due to this configuration, it becomes possible to detect 1 bit of data error. This RAS function, which is referred to as a parity check function, is suitable for cases in which the frequency of data error occurrence is low, and even if several error bits occur, there is no tendency for that error to be concentrated at neighboring bits, and it is also suitable for cases in which an error may be recovered by performing an operation again or by obtaining the data again. This parity check function is often used for circuits that do not use many resources or execution latency for the RAS circuit (for example, a functional unit).
On the other hand, registers that require the self repair of data are often provided with an RAS function that is capable of not only detecting an error but also correcting an error. For example, a 1 bit of error correction (SEC: Single bit Error Correct) circuit for 32 bits of information data may realize the RAS function by adding 6 check bits to the information data as a redundant portion (for example, a Hamming code). Moreover, if an extended Hamming code where the number of check bits is further increased by 1 bit is used, the function of 2 bits of error detection and 1 bit of error correction (SECDED: Single bit Error Correct and Double bit Error Detect) may be realized. However, circuits that realize such RAS functions involve a large number of elements compared with data error detectors that use the above-mentioned parity check, and thus the detection and correction of a data error causes a certain degree of latency.
In relation to the above-mentioned RAS function, some techniques are known.
One such technique is to generate data with error detection/correction code using a simple configuration. In this technique, data with an error detection bit includes m bytes of an information portion of which each byte has n bits as well as a redundant portion of m bits of error detection provided in the m bytes of the information portion, and an exclusive-OR operation is firstly performed on the m bytes of the information portion of the data with error detection bits. Then, a portion of log2 (n+1) bits is generated from the redundant portion of the data with error detection/correction code, and the generated portion and the error detection bit are input to generate other portions of m bits.
Another one of such techniques is to provide a memory with a parity check function and an SECDED capability, and to use one of the parity check function and the SECDED capability depending on a control signal.
Note that the techniques disclosed in the following documents are also known.                Document 1: Japanese Laid-open Patent Publication No. 2011-109476        Document 2: Japanese Laid-open Patent Publication No. 56-094596        
There are also some cases in which the capability of an RAS function needs to be improved in existing circuits in which the RAS function has already been installed in order to deal with, for example, the increase in software errors caused due to fine processing technology.
FIG. 1 will be explained below. FIG. 1 illustrates an example of the configuration of a processor having a parity check function.
The processor 1 of FIG. 1 includes a functional unit 2, a general purpose register (GPR) 3, and a 1-bit error detector 4.
The functional unit 2 internally includes a parity bit generation circuit and a parity check circuit for a parity check function. Data with a parity bit is input to or output from the functional unit 2. Note that the data with the parity bit is the data that includes information unit data in which the original information of the data is contained and a parity bit of the information unit data.
Regarding the information unit data, it is assumed in the following explanations that each byte is configured by n bits of data, and that the number of bytes is m (note that both m and n indicate an integer that is equal to or larger than 1). Moreover, it is assumed that the data with a parity bit includes 1 parity bit for every 1 byte that constitutes the information unit data. In other words, it is assumed that the data with a parity bit includes m*n bits of information unit data and n parity bits.
The general purpose register 3 includes a plurality of registers in which the data with a parity bit that is input to or output from the functional unit 2 is stored. In FIG. 3, “data” indicates the region in which the information unit data is stored, and “p” indicates the region in which the parity bit is stored.
The 1-bit error detector 4 is a circuit that performs a parity check to detect an error in the data with a parity bit, which is read from the general purpose register 3 by the functional unit 2. More specifically, the 1-bit error detector 4 is a circuit that performs an XOR operation for each m bytes of data between n pieces of bit data constituting 1 byte of data in the data with a parity bit and a parity bit for the 1 byte of data.
When arithmetic processing is performed in the processor 1 of FIG. 1, the functional unit 2 firstly reads the data with a parity bit, which includes the information unit data to be processed, from the general purpose register 3. At the same time, the 1-bit error detector 4 performs a parity check on the data with a parity bit, which is read from the general purpose register 3 by the functional unit 2.
Here, if a data error is detected in the data with a parity bit, the 1-bit error detector 4 outputs an error detection signal, which indicates the detection of a data error, as an “error report”. A controller (not illustrated) that controls the processor 1 of FIG. 1 performs control processing for recovering the error in the data with a parity bit stored in the general purpose register 3 when an error detection signal output from the 1-bit error detector 4 is received. More specifically, once an error detection signal is received, the controller controls the processor 1 to read again from the general purpose register 3 the data with a parity bit in which a data error is detected. Then, the controller controls the functional unit 2 to store the obtained data with a parity bit in the general purpose register 3.
On the other hand, the functional unit 2 may independently perform a parity check on the data with a parity bit read from the general purpose register 3. When no error is detected, the functional unit 2 retrieves the information unit data from the data with a parity bit read from the general purpose register 3 to perform arithmetic processing, thereby obtaining the data of an operation result. Then, a parity bit is generated for the data of an operation result, and the data with a parity bit obtained by adding the generated parity bit to the data of an operation result is stored in the general purpose register 3.
Here, a technique of changing the parity check function of the processor 1 into the SEC capability or the SECDED capability with the purpose of improving the RAS function provided for the processor 1 of FIG. 1 will be discussed.
FIG. 2 will be explained below. FIG. 2 illustrates an example of the configuration of a processor in which the RAS function is improved on the processor 1 of FIG. 1.
In a processor 5 of FIG. 2, the 1-bit error detector 4 is deleted from the existing configuration of FIG. 1, and an error detection/correction circuit 6, a parity generation circuit 7, and an ECC (Error Correcting Code) generation circuit 8 are additionally comprised. Moreover, in the processor 5, instead of the data with a parity bit, data with ECC, which is the information unit data to which an ECC used for the SEC capability or the SECDED capability is added, is stored in the general purpose register 3.
The error detection/correction circuit 6 receives the data with ECC that is read from the general purpose register 3 by the functional unit 2, and detects and corrects an error in the data with ECC by using the ECC included therein. When an error is corrected, the error detection/correction circuit 6 stores the corrected data with ECC in the general purpose register 3 in which the data with ECC was stored.
The parity generation circuit 7 receives error-free data with ECC from the error detection/correction circuit 6, and generates a parity bit for the information unit data included in the data with ECC. Then, the parity generation circuit 7 inputs to the functional unit 2 the data with a parity bit obtained by adding the parity bit to the information unit data. Due to the provision of the parity generation circuit 7, it becomes unnecessary to change the circuitry of the existing functional unit 2 in order to change the parity check function.
The ECC generation circuit 8 generates an ECC, which is used for the SEC capability or the SECDED capability, from the entirety of the m bytes of information unit data included in the data with a parity bit that is output from the functional unit 2 so as to store the result of arithmetic processing in the general purpose register 3. Then, the data with ECC is obtained by adding the generated ECC to the data of an operation result that is included in the data with a parity bit output from the functional unit 2, and the obtained data with ECC is stored in the general purpose register 3.
In the configuration of the processor 5 of FIG. 2, the error detection/correction circuit 6, the parity generation circuit 7, and the ECC generation circuit 8 are inserted between the functional unit 2 and the general purpose register 3. For this reason, latency may be caused in the data transfer between the functional unit 2 and the general purpose register 3.
Moreover, in the configuration of the processor 5 of FIG. 2, it is necessary for the general purpose register 3 to store the data with ECC of which the number of bits is larger than that of the data with a parity bit.
For example, it is assumed that the information unit data is the data where each byte is configured by 8 bits of data and the number of bytes is four, i.e., it is assumed that the information unit data is the data where there are thirty two bits. In this case, the number of parity bits included in the data with a parity bit is four. Here, if it is desired that the SEC capability for 32 bits of information unit data be realized, the number of bits of the ECC needs to be at least six. Moreover, if it is desired that the SECDED capability for 32 bits of information unit data be realized, there needs to be at least seven bits of the ECC.
As described above, if the RAS function is upgraded from a parity check to an SEC capability or an SECDED capability, the number of bits of the redundant data required for the RAS function increases. For this reason, if the configuration of FIG. 1 is changed to the configuration of FIG. 2, the general purpose register 3 maybe replaced so as to be capable of storing a larger number of bits. As described above, it is necessary to make a significant change to the existing configuration of the processor 1 of FIG. 1 if it is desired to configure the processor 5 of FIG. 2.